Referring to FIG. 1, there is shown a basic network architecture in accordance with the prior art. A computer or other network device 50 communicates with other network devices by sending packets of information 52 through a router 54. Each packet 52 includes a header indicating basic information such as the source of the packet (for example computer 50a) or source address (SA) and a destination of the packet (for example computer 50b) or destination address (DA). Router 54 receives each packet, determines the SA and DA, and forwards each packet to its appropriate destination.
Routers typically operate at the Data Link layer (“layer 2”) of the Open Systems Interconnection (“OSI”) model. Their operation is defined in the American National Standards Institute (“ANSI”) Institute of Electrical and Electronics Engineers (“IEEE”) 802.1D standard. A copy of the ANSI/IEEE Standard 802.1D, 1998 Edition, is incorporated by referenced herein in its entirety.
Telecommunication traffic among network devices is divided into seven layers under the OSI model and the layers themselves split into two groups. The upper four layers are used whenever a message passes to or from a user. The lower three layers are used when any message passes through the host computer, whereas messages intended for the receiving computer pass to the upper four layers. “Layer 2” refers to the data-link layer, which provides synchronization for the physical level and furnishes transmission protocol knowledge and management.
Referring to FIG. 2, router 54 may include a media access controller “MAC” 60, a packet processor 62, a content addressable memory (“CAM”) 80, a random access memory including parameter information (“PRAM”) 70, and a transmission manager 66 coupled through a bus 74 and controlled by a processor 72. MAC 60 is an interface by which data in the form of packets is transmitted to and received from router 54. MAC 60 performs any data conversions needed for the packets to later be processed by packet processor 62. Received packets 52 are forwarded by MAC 60 to packet processor 62. For example, if the packets are in the form of 32 bit double data rate data and packet processor 62 processes 64 bit single data rate data, MAC 60 performs the needed conversion. Packet processor 62 acts as a conduit between operations performed inside router 54 and MAC 60. For example, packet processor 62 extracts the DA and SA from a received packet.
CAM 80 receives the DA and SA of a received packet forwarded from packet processor 62 and compares this information with information stored within CAM 80. If the DA and SA matches an entry in CAM 80, additional forwarding information regarding the disposition of the received packet is available from PRAM 70 and is retrieved for incorporation into the header of the packet. For example, information such as destination port of the packet, port mirror requirement, packet type, VLAN handling information, prioritization, multicast group member ship, etc., may be included in PRAM 70. The received packet is reformatted with a new header using the PRAM information. If the header information in the received packet does not match information in memory 80, forwarding information is appended directing the packet to a system manager interface (not shown) for additional processing.
Current packet formatting standards are moving from Internet Protocol version 4 (IPV4) to Internet Protocol version 6 (IPV6). IPV4 includes a lookup table of 128 bits whereas IPV6 has a table of 320 bits. A typical CAM is 64 bits wide so it can receive 64 bits at one time. To handle the increased table requirements of IPV6, a conventional approach may be to simply to use the same cycle timing and run the CAM faster so that processing even with the extra cycles may be performed in a desired time period. Such a solution may work in applications which use ASIC (application specific integrated circuits). However, in CAMs which use a field programmable gate arrays (FPGA), simply running the CAM faster is not available. Yet, use of a FPGA is sometimes desirable as they are easier to use and program, more readily available, and easier to modify.
Due to the increased demands of IPV6, it is desirable to reduce the number of cycles used by a CAM and thereby increase processing speed. Therefore, there is a need in the art for a system and method for optimizing the lookup timing of a CAM without simply forcing the CAM to run faster.